Entry Level RTL Design Engineer
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Verilog
System Verilog
Python
UVM
C++
I am currently in my final semester and looking for entry level job in RTL design or in design verification. I have good understanding in ASIC design, synthesis and UVM. I am a F1 student and would require sponsorhip in future, please feel free to contact me to discuss further about my qualification. Looking forward to connect with you all.